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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Phase assignment method for virtual-wire-based hardware emulation

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12835

    Title: Phase assignment method for virtual-wire-based hardware emulation
    Authors: Su,Hsiao-Pin
    Date: 1997
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Keywords: Integrated circuit layout
    Logic design
    Time division multiplexing
    Problem solving
    Heuristic methods
    Abstract: In a hardware emulator consisting of multiple field-programmable gate arrays (FPGA's), the utilization of the FPGA logic resource is usually very low due to the limitation on the number of I/O pins. Virtual wire technology not only increases the inter-FPGA communication capability, but it also increases the logic resource utilization by means of time division multiplexing (TDM). TDM allows one physical wire to be shared by multiple logical wires. For TDM to be effective, each transportation of an inter-FPGA signal must be carefully assigned to a slot of the time division. In this note, we show that the phase assignment problem is exactly same as the resource-constrained operation scheduling problem. We adopt the static-list scheduling heuristic for the task, and present some experimental results on a set of benchmark circuits from the MCNC. The experiments show that the proposed method can increase the number of effective I/O pins as many as ten times.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12835
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [清大/工研院聯合研究中心] 期刊論文

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