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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12837

    Title: TRACER-fpga: A Router for RAM-Based FPGAs
    Authors: Chen,Ching-Dong
    Wu,Allen C. -H
    Date: 1995
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Keywords: Logic gates
    Random access storage
    Cellular arrays
    Graph theory
    Simulated annealing
    Mathematical models
    Application specific integrated circuits
    Rapid prototyping
    Electric wiring
    Computer aided logic design
    Abstract: We describe a routing method for the design of a class of RAM-based field programmable gate arrays (FPGA). We model the interconnect resources as a graph. A routing solution is represented as a set of disjoint trees, each connecting all terminals of a net, on the graph. An expansion router is used for connecting a net. Initially, nets are connected independently of one another. Conflicts among nets over the usage of interconnect resources are resolved iteratively by a rip-up and rerouter, which is guided by a simulated evolution-based optimization technique. The proposed approach has been implemented in a program called TRACER-fpga. As compared with CGE and SEGA, TRACER-fpga in general requires fewer routing tracks at the expense of longer wiring delay. It is suitable for low-speed applications such as hardware emulation.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12837
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [清大/工研院聯合研究中心] 期刊論文

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