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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12979


    Title: A BIST scheme for FPGA interconnect delay faults
    Authors: Chun-Chieh Wang
    Jing-Jia Liou
    Yen-Lin Peng
    Chih-Tsun Huang
    Cheng-Wen Wu
    Date: 2005
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Keywords: built-in self test
    clocks
    fault diagnosis
    field programmable gate arrays
    integrated circuit interconnections
    Abstract: In this paper, we propose a new BIST-based approach for testing FPGA interconnect delay faults. The BIST architecture utilizes the regularity of an FPGA by implementing small test circuits repetitively over FPGA's CLB arrays. Each test circuit targets a specific path and determine conformance of the path delay according to a test clock. With the target path configured as a loop back in the test circuit, test accuracy of the path delay can be increased with reduced effects from skews of the test clocks. Thus, this BIST has a higher delay fault coverage, since it is not necessary to apply guard bands for skews in test mode.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12979
    Appears in Collections:[電機工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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