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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  Analysis of delay test effectiveness with a multiple-clock scheme

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12986

    Title: Analysis of delay test effectiveness with a multiple-clock scheme
    Authors: Jing-Jia Liou
    Wang, L.-C.
    Kwang-Ting Cheng
    Dworak, J.
    Mercer, M.R.
    Kapur, R.
    Williams, T.W.
    教師: 劉靖家
    Date: 2002
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Relation: Test Conference, 2002. Proceedings. International
    7-10 Oct. 2002 Page(s):407 - 416
    Keywords: VLSI
    automatic test pattern generation
    integrated circuit testing
    logic testing
    Abstract: In conventional delay testing, two types of tests, transition tests and path delay tests, are often considered. The test clock frequency is usually set to a single pre-determined parameter equal to the system clock. This paper discusses the potential of enhancing test effectiveness by using multiple test sets with multiple clock frequencies. The two intuitions motivating our analysis are 1) multiple test sets can deliver higher test quality than a single test set, and 2) for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out potentially defective chips. Hence, by using multiple test sets, the overall quality of AC delay test can be enhanced, and by using multiple-clock schemes the cost of adding the additional pattern sets can be minimized. In this paper, we analyze the feasibility of this new delay test methodology with respect to different combinations of pattern sets and to different circuit characteristics. We discuss the pros and cons of multiple-clock schemes through analysis and experiments using a statistical delay evaluation and delay defect-injected framework.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12986
    Appears in Collections:[電機工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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