We summarize the experience of estimating the average power dissipation of a security processor (of 430K gates) using an in-house tool, called ToggleFinder. The estimation is done at the register-transfer level (RTL) so that the CPU time can be slashed dramatically. At the same time, the accuracy is retained by two techniques: power mode classification and scalable linear approximation. We found that a security processor containing a number of different encryption and decryption schemes, such as AES and RSA, could consume power very differently from one clock cycle to another. Also, the design gate count of a design block does not reflect how much power it consumes very well. Such a large design demonstrates that our new power estimation method is truly useful in a low-power design process.