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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  An ATPG-based framework for verifying sequential equivalence

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13023

    Title: An ATPG-based framework for verifying sequential equivalence
    Authors: Shi-Yu Huang
    Kwang-Ting Cheng
    Kuang-Chien Chen
    Glaeser, U.
    教師: 黃錫瑜
    Date: 1996
    Publisher: Institute of Electrical and Electronics Engineers Computer Society
    Relation: Test Conference, 1996. Proceedings., International
    20-25 Oct. 1996 Page(s):865 - 874
    Keywords: ATPG
    sequential circuits
    Abstract: In this paper, we address the problem of verifying the equivalence of two sequential circuits. State-of-the-art sequential optimization techniques such as retiming and sequential redundancy removal can handle designs with up to hundreds or even thousands of flip-flops. The BDD-based approaches for equivalence checking can easily run into memory explosion for such designs. With an attempt to handle larger circuits, we modify the test pattern generation techniques for verification. The suggested approach utilizes the efficient backward justification technique popularly used in most sequential ATPG programs. The method explores the structural similarity between circuits under verification, and performs the verification in stages to improve the efficiency. An effective algorithm to identify equivalent hip-hops is presented. This ATPG-based framework is suitable for verifying circuits with or without a reset state. Experimental results of verifying the correctness of circuits after sequential redundancy removal are presented.
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13023
    Appears in Collections:[電機工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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