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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  AQUILA: An equivalence verifier for large sequential circuits

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13032

    Title: AQUILA: An equivalence verifier for large sequential circuits
    Authors: Shi-Yu Huang
    Kwang-Ting Cheng
    Kuang-Chien Chen
    教師: 黃錫瑜
    Date: 2007
    Publisher: Institute of Electrical and Electronics Engineers
    Keywords: AQUILA
    Abstract: In this paper, we address the problem of verifying the equivalence of two sequential circuits. A hybrid approach that combines the advantages of BDD-based and ATPG-based approaches is introduced. Furthermore, we incorporate a technique called partial justification to explore the sequential similarity between the two circuits under verification to speed up the verification process. Compared with existing approaches, our method is much less vulnerable to the memory explosion problem, and therefore can handle larger designs. The experimental results show that in a few minutes of CPU time, our tool can verify the sequential equivalence of an intensively optimized benchmark circuit with hundreds of flip-flops against its original version.
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13032
    Appears in Collections:[電機工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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