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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  An access timing measurement unit of embedded memory

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13445

    Title: An access timing measurement unit of embedded memory
    Authors: Shu-Rong Lee
    Ming-Jun Hsiao
    Tsin-Yuan Chang
    教師: 張慶元
    Date: 2002
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Relation: Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian 18-20 Nov. 2002 Page(s):104 - 109
    Keywords: CMOS integrated circuits
    built-in self test
    integrated circuit measurement
    integrated circuit testing
    Abstract: As deep sub-micron techniques evolve, embedded memories are dominating the yield, while the testing and measurement issues are more difficult due to access limitations. To solve the testing problem, BIST circuits are developed for testing the functionality of embedded memory, but not for the AC parameters. Based on the dual-slope principle, a new memory access time measurement unit for embedded memories with separate time-to-voltage and voltage-to-time architecture is proposed in this paper to achieve at-speed measurement with 50 ps resolution, where the measurement error is smaller than one LSB, and the linearity error is 1.19%. In conjunction with the March-based BIST circuit, the chip area is 262/spl times/92 /spl mu/m/sup 2/ under a 0.35 /spl mu/m 2P4M CMOS process.
    Relation Link: http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13445
    Appears in Collections:[電機工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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