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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13547


    Title: Architecture driven circuit partitioning
    Authors: Chen,Chau-Shen
    Hwang,TingTing
    Liu,C. L.
    教師: 黃婷婷
    Date: 1998
    Publisher: Institute of Electrical and Electronics Engineers Computer Society
    Relation: Computer-Aided Design,1998.ICCAD 98.Digest of Technical Papers.1998 IEEE/ACM International Conference, 8-12 Nov 1998, Page(s):408-411
    Keywords: Field programmable gate arrays
    Computer aided logic design
    Algorithms
    Microprocessor chips
    Functions
    Abstract: In this paper, we propose an architecture driven partitioning algorithm for netlists with multi-terminal nets. Our target architecture is a multi-FPGA emulation system with folded-Clos network for board routing. Our goal is to minimize the number of FPGA chips used and maximize the routability. To that end, we introduce a new cost function: the average number of pseudo terminals per net in a multi-way cut. Experiment result shows that our algorithm is very effective in terms of the number of chips used and the routability as compared to other methods.
    Relation Link: http://ieeexplore.ieee.org/search/srchabstract.jsp?arnumber=742905&isnumber=16008&punumber=5975&k2dockey=742905@ieeecnfs&query=%28%28architecture+driven+circuit+partitioning%29%3Cin%3Emetadata%29&pos=1
    http://ieeexplore.ieee.org/Xplore/dynhome.jsp
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13547
    Appears in Collections:[資訊工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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