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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  An AVPG for SOC design verification with port order fault model

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13645

    Title: An AVPG for SOC design verification with port order fault model
    Authors: Chun-Yao Wang
    Shing-Wu Tung
    Jing-Yang Jou
    教師: 王俊堯
    Date: 2001
    Publisher: Institute of Electrical and Electronics Engineers Computer Society
    Relation: Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
    Volume 5, 6-9 May 2001 Page(s):259 - 262 vol. 5
    Keywords: port order fault
    automatic verification pattern generation
    Abstract: Embedded cores are being increasingly used in the design of large system-on-a chip (SoC). Because the high complexity of SoC, the design verification is a challenge for system integrator. To reduce the verification complexity, the port order fault (POF) model has been used for verifying the core-based design. In this paper, we present a verification scheme and an automatic verification pattern generation (AVPG) system based on POF model
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13645
    Appears in Collections:[資訊工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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