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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  Board-level multi-terminal net routing for FPGA-based logic emulation

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13674

    Title: Board-level multi-terminal net routing for FPGA-based logic emulation
    Authors: Mak,Wai-Kei
    Wong,D. F.
    教師: 麥偉基
    Date: 1995
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: ICCAD-95. Digest of Technical Papers.,1995 IEEE/ACM International Conference on 5-9 Nov. 995 Page(s):339-344
    Keywords: Logic gates
    Problem solving
    Mathematical models
    Logic design
    Abstract: We consider a board-level routing problem applicable to FPGA-based logic emulation systems such as the Realizer System and the Enterprise Emulation System manufactured by Quickturn Systems. Optimal algorithms have been proposed for the case where all nets are two-terminal nets. In this paper, we show how multi-terminal nets can be handled by decomposition into two-terminal nets. We show that the multi-terminal net decomposition problem can be modelled as a bounded-degree hypergraph-to-graph transformation problem where hyperedges are transformed to spanning trees. A network flow-based algorithm that solves both problems is proposed. It determines if there is a feasible decomposition and gives one whenever such a decomposition exists.
    Relation Link: http://ieeexplore.ieee.org/Xplore/dynhome.jsp
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13674
    Appears in Collections:[資訊工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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