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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  Accurate and efficient inductance extraction for SoC noise and signal integrity

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13810

    Title: Accurate and efficient inductance extraction for SoC noise and signal integrity
    Authors: Li-Fu Chang
    Chang, K.-J.
    Date: 2002
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Keywords: circuit simulation
    computational electromagnetics
    eddy currents
    high-speed integrated circuits
    integrated circuit interconnections
    integrated circuit modelling
    integrated circuit noise
    skin effect
    Abstract: With the advent of 500 MHz+ SoC designs, recent intensive on-chip inductance research and publications from academia and semiconductor industry have resulted in early adoptions of interconnect inductance extraction tools by state-of-the-art SoC designers for noise and signal integrity modeling. For those early tool developers and adopters, we propose a set of comprehensive criteria toward an on-chip inductance gold standard to insure accuracy. The three essential criteria for an inductance gold standard we propose are: (1) accurate partial inductance formulae; (2) rigorous 3-D electromagnetic field simulations; (3) comprehensive eddy-current-limited loop and mutual inductance extraction. After brief descriptions of three widely used empirical inductance modeling equations, the necessity of a PEEC-based 3-D electromagnetic field simulation is explained by using nanometer-technology-based SoC interconnect cases. For accurate noise and signal integrity predictions, synthesizing RLCK netlists for SPICE-level circuit simulators is then performed to depict the effects caused by the eddy-current-limited loop and mutual inductance extracted using the gold standard.
    Relation Link: http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13810
    Appears in Collections:[資訊工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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