National Tsing Hua University Institutional Repository:A 3-Step Approach for Performance-Driven Whole Chip Routing
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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  A 3-Step Approach for Performance-Driven Whole Chip Routing


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    题名: A 3-Step Approach for Performance-Driven Whole Chip Routing
    作者: Yih-Chih Chou
    Youn-Long Lin
    日期: 2001
    出版者: Institute of Electrical and Electronics Engineers Computer Society
    关键词: circuit layout CAD
    integrated circuit layout
    network routing
    trees
    摘要: We propose a 3-step approach for whole-chip detail routing. In the first step, we construct a performance-driven Steiner tree for each net ignoring the existence of other nets. In the second step, we optimally assign significant wire segments of all trees to the tracks of a two-dimensional, two-layer grid under the design rule constraint. Finally, in the third step, we complete the remaining local short connection between net terminals and those assigned wire segments and resolve any violations or congestion. We have incorporated this approach into an industrial VDSM design flow. Experimental results on large benchmark circuits implemented in a TSMC 0.18 μm CMOS process have demonstrated the effectiveness of the proposed approach. We achieve more than 14% improvement over a state-of-art commercial performance-driven router in critical path delay. Our tool can be viewed as a preprocessor for a router. Users do not have to change their existing design flow. Only a small time-efficient step is needed to achieve the performance gain
    相関连結: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/14065
    显示于类别:[資訊工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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