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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  Automatic generation of memory built-in self-test cores for system-on-chip

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/14236

    Title: Automatic generation of memory built-in self-test cores for system-on-chip
    Authors: Cheng,Kuo-Liang
    教師: 黃稚存
    Date: 2001
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: Test Symposium,2001.Proceedings.10th Asian,19-21 Nov.2001, Page(s):91-96
    Keywords: VLSI
    application specific integrated circuits
    automatic test pattern generation
    built-in self test
    circuit CAD
    high level synthesis
    integrated circuit design
    integrated circuit testing
    integrated memory circuits
    logic testing
    microprocessor chips
    random-access storage
    Abstract: Memory testing is becoming the dominant factor in testing a system-on-chip (SoC), with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SoC designs. The BIST generation framework is a much improved one of our previous work. Test integration of heterogeneous memory architectures and clusters of memories are focused on. The automatic test grouping and scheduling optimize the overhead in test time, performance, power consumption, etc. Furthermore, with our novel BIST architecture, the BIST cores can be accessed via an on-chip bus interface (e.g., AMBA), which eases the control of testing and diagnosis in a typical SoC scenario. With a configurable and extensible architecture, the proposed framework facilitates easy memory test integration for core providers as well as system integrators
    Relation Link: http://ieeexplore.ieee.org/Xplore/dynhome.jsp
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/14236
    Appears in Collections:[資訊工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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