National Tsing Hua University Institutional Repository:A 1.2-V 0.25-mu m clock output pixel architecture with wide dynamic range and self-offset cancellation
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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  A 1.2-V 0.25-mu m clock output pixel architecture with wide dynamic range and self-offset cancellation


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    題名: A 1.2-V 0.25-mu m clock output pixel architecture with wide dynamic range and self-offset cancellation
    作者: Lai CH;King YC;Huang SY
    教師: 金雅琴
    日期: 2006
    出版者: Institute of Electrical and Electronics Engineers
    關聯: IEEE SENSORS JOURNAL,Volume 6,Issue 2,Pages 398-405 ,APR 2006
    關鍵詞: CMOS IMAGE SENSOR
    LEVEL ADC
    摘要: © 2006 Institute of Electrical and Electronics Engineers-A 10T/pixel CMOS digital pixel sensor with clock count output, ultra low supply voltage, and wide dynamic range is presented. The pixel fabricated by a standard 0.25-mu m CMOS logic process comprises a reset transistor, a photo-diode, a comparator, and an inverter with pixel size of 9.4 x 9.4 mu m(2) and 24% fill factor. The amplified logarithmic output response similar to the light response of human eye is demonstrated in this work. The pixel can operate at a supply voltage as low as 1.2 V without affecting its output characteristics. The dynamic range of this cell limited by either the subsequent analog-to-digital circuit resolution or the rising and falling time of output clock is higher than 90 dB with an 8-bit resolution.
    URI: http://www.ieee.org/
    http://nthur.lib.nthu.edu.tw/handle/987654321/42319
    顯示於類別:[電機工程學系] 期刊論文

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