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    顯示項目1-25 / 362. (共15頁)
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    日期題名作者
    2005 1 Tbits/in.^2 非暫存式資料儲存:靜電力掃瞄探針陣列晶片之設計與製作(I) 盧向成
    2004 A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications Huang, Yuan-Hao; Ma, Hsi-Pin; Liou, Ming-Luen; Chiueh, Tzi-Dar
    2006 A 1.2-V 0.25-/spl mu/m clock output pixel architecture with wide dynamic range and self-offset cancellation Lai,Cheng-Hsiao; King,Ya-Chin; Huang,Shi-Yu
    1999 1.3μm波長GaInP/InAsP/InP雷射二極體之研製 吳孟奇
    2003 1.3微米波長增益耦合與複式耦合電流阻隔式光柵砷化鋁鎵銦多重量子井分佈回授型半導體雷射(I) 吳孟奇
    2004 1.3微米波長增益耦合與複式耦合電流阻隔式光柵砷化鋁鎵銦多重量子井分佈回授型半導體雷射(II) 吳孟奇
    2005 1.55 .mu.m 共振腔發光二極體與垂直式共振腔面射型雷射之研製(I) 吳孟奇
    2004 A 123-mW W-CDMA uplink baseband receiver IC with beamforming capability Hsi-Pin Ma; Ming-Luen Liou; Tzi-Dar Chiueh
    1997 A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrum transceiver IC [wireless LANs] Wu,Jen-Shi; Liou,Ming-Luen; Ma,Hsi-Pin; Chiueh,Tzi-Dar
    2000 AGCVD鋁在雙層金屬系統的電遷移 葉鳳生
    2000 AQUILA: An equivalence checking system for large sequential designs Huang,Shi-Yu; Cheng,Kwang-Ting; Chen,Kuang-Chien; Huang,Chung-Yang; Brewer,Forrest
    1999 AutoFix: A Hybrid Tool for Automatic Logic Rectification Shi-Yu Huang; Kuang-Chien Chen; Kwang-Ting Cheng
    2003 Automatic interconnection rectification for SoC design verification based on the port order fault model Wang,Chun-Yao; Tung,Shing-Wu; Jou,Jing-Yang
    2002 An automorphic approach to verification pattern generation for SoC design verification using port-order fault model Wang,Chun-Yao; Tung,Shing-Wu; Jou,Jing-Yang
    1997 Boolean matching for incompletely specified functions Wang,Kuo-Hua; Hwang,TingTing
    2004 A built-in parametric timing measurement unit Hsiao, Ming-Jun; Huang, Jing-Reng; Chang, Tsin-Yuan
    2007 Built-In Self-Repair for Die-to-Die Misalignment of Multidie Space Sensors Chun-Fu Chen; Shi-Yu Huang; Ya-Chin King
    2001 A built-in timing parametric measurement unit Hsiao, Ming-Jun; Huang, Jing-Reng; Yang, Shao-Shen; Chang, Tsin-Yuan
    2007 A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design Wen-Wen Hsieh; Po-Yuan Chen; Chun-Yao Wang; TingTing Hwang
    1996 Cell height driven transistor sizing in a cell based static CMOS module design How-Rern Lin; Yu-Chin Hsu; TingTing Hwang
    1991 Channel density reduction by routing over the cells Lin,Min-Siang; Perng,Hourng-Wern; Hwang,Chi-Yi; Lin,Youn-Long
    2001 Charge-sharing alleviation and detection for CMOS domino circuits Shih-Chieh Chang; Ching-Hwa Cheng; Wen-Ben Jone; Shin-De Lee; Jinn-Shyan Wang
    1999 Circuit optimization by rewiring Chang,Shih-Chieh; van Ginneken, Lukas P.P.P.; Marek-Sadowska,Malgorzata
    2005 Code-pattern insensitive embedded ROMs using dynamic bitline shielding technique Chang, M.-F.; Chiou, L.-Y.; Wen, K.-A.
    1991 Combining logic minimization and folding for PLAs Hsu,Yu-Chin; Lin,Youn-Long; Hsieh,Hang-Ching; Chao,Ting-Hai

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