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    National Tsing Hua University Institutional Repository > 工學院  > 工業工程與工程管理學系 > 會議論文  >  Optimize die size design to enhance owe for design for manufacturing

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/46414

    Title: Optimize die size design to enhance owe for design for manufacturing
    Authors: Chen-Fu Chien;Chia-Chih Liu;Chia-Yu Hsu;Hong-Shing Chou;Chih-Wei Lin
    教師: 簡禎富
    Date: 2007
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: 2007 International Symposium on Semiconductor Manufacturing, Santa Clara, CA, USA, 15-17 Oct. 2007, Pages 142-145
    Keywords: cost reduction
    integrated circuit design
    Abstract: To enhance competitive advantages, it is crucial for wafer fabs to reduce average die cost through productivity improvement via increasing the number of gross dies per wafer and throughput. However, gross die number is influenced by die size in design phase, while the existing size of integrated circuit die was designed without considering the effect on wafer throughput in fabrication phase. This research aims to develop a die size optimization algorithm based on decision tree to construct the rules between the number of gross dies per wafer, mask utilization, and the die feature including length, width, and area. Without losing generality, an empirical study has been done for validation by using transformed data from a fab in Taiwan.
    URI: http://www.ieee.org/
    Appears in Collections:[工業工程與工程管理學系] 會議論文

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