National Tsing Hua University Institutional Repository:Through-Silicon Via Planning in 3-D Floorplanning
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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Through-Silicon Via Planning in 3-D Floorplanning


    題名: Through-Silicon Via Planning in 3-D Floorplanning
    作者: Tsai, M.-C.;Wang, T.-C.;Hwang, T. T.
    教師: 王廷基
    日期: 2011
    出版者: Institute of Electrical and Electronics Engineers
    關聯: Very Large Scale Integration (VLSI) Systems,IEEE Transactions on,Issue Date: Aug. 2011,Volume: 19,Issue:8,On page(s): 1448 - 1457
    關鍵詞: Through-Silicon
    3-D Floorplanning
    摘要: In this paper, we will study floorplanning in 3-D integrated circuits (3D-ICs). Although literature is abundant on 3D-IC floorplanning, none of them consider the areas and positions of signal through-silicon vias (TSVs). In previous research, signal TSVs are viewed as points during the floorplanning stage. Ignoring the areas, positions and connections of signal TSVs, previous research estimates wirelength by measuring the half-perimeter wirelength of pins in a net only. Experimental results reveal that 29.7% of nets possess signal TSVs that cannot be put into the white space within the bounding boxes of pins. Moreover, the total wirelength is underestimated by 26.8% without considering the positions of signal TSVs. The considerable error in wirelength estimation severely degrades the optimality of the floorplan result. Therefore, in this paper, we will propose a two-stage 3-D fixed-outline floorplaning algorithm. Stage one simultaneously plans hard macros and TSV-blocks for wirelength reduction. Stage two improves the wirelength by reassigning signal TSVs. Experimental results show that stage one outperforms a post-processing TSV planning algorithm in successful rate by 57%. Compared to the post-processing TSV planning algorithm, the average wirelength of our result is shorter by 22.3%. In addition, stage two further reduces the wirelength by 3.45% without any area overhead.
    顯示於類別:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文


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