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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  Power estimation strategies for a low-power security processor

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/66919

    Title: Power estimation strategies for a low-power security processor
    Authors: Y.F. Lin;S.Y. Huang;S.Y. Hsu;I.L. Chen;C.T. Hsieh;J.C. Lin;S.C. Chang
    教師: 張世杰
    Date: 2005
    Relation: Design Automation Conference,2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific,Issue Date: 18-21 Jan. 2005,On page(s): 367 - 371 Vol. 1
    Keywords: Power estimation strategies
    low-power security processor
    Abstract: In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the logic part, we present a highly accurate tool, called PowerMixer. This tool is a refinement of the so-called mixed-level methodology that combines the accuracy of quick SPICE and the speed of gate-level simulation. A grouping scheme is proposed so as to improve the accuracy for design blocks as large as 100K gates. For the memory part, we investigated the power consuming behavior of memories and point out the potential problems associated with the current commercial design flow. These tools, along with a previously published static peak power estimation method (Hsieh et al., 2004), jointly provide an evaluation platform for the power optimization and verification process of our security processor in a practical way.
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/66919
    Appears in Collections:[資訊工程學系] 會議論文

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