National Tsing Hua University Institutional Repository:Power estimation strategies for a low-power security processor
English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 54367/62174 (87%)
造訪人次 : 14937080      線上人數 : 35
RC Version 6.0 © Powered By DSPACE, MIT. Enhanced by NTHU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  Power estimation strategies for a low-power security processor


    題名: Power estimation strategies for a low-power security processor
    作者: Y.F. Lin;S.Y. Huang;S.Y. Hsu;I.L. Chen;C.T. Hsieh;J.C. Lin;S.C. Chang
    教師: 張世杰
    日期: 2005
    關聯: Design Automation Conference,2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific,Issue Date: 18-21 Jan. 2005,On page(s): 367 - 371 Vol. 1
    關鍵詞: Power estimation strategies
    low-power security processor
    摘要: In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the logic part, we present a highly accurate tool, called PowerMixer. This tool is a refinement of the so-called mixed-level methodology that combines the accuracy of quick SPICE and the speed of gate-level simulation. A grouping scheme is proposed so as to improve the accuracy for design blocks as large as 100K gates. For the memory part, we investigated the power consuming behavior of memories and point out the potential problems associated with the current commercial design flow. These tools, along with a previously published static peak power estimation method (Hsieh et al., 2004), jointly provide an evaluation platform for the power optimization and verification process of our security processor in a practical way.
    顯示於類別:[資訊工程學系] 會議論文


    檔案 描述 大小格式瀏覽次數


    SFX Query


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 回饋