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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  An efficient multi-mode multiplier supporting AES and fundamental operations of public-key cryptosystems

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83577

    Title: An efficient multi-mode multiplier supporting AES and fundamental operations of public-key cryptosystems
    Authors: C.-H. Wang;C.-L. Chuang;C.-W. Wu
    教師: 吳誠文
    Date: 2010
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Institute of Electrical and Electronics Engineers, Volume 18, Issue 4, APR 2010, Pages 553 - 563
    Keywords: multi-mode
    Abstract: This paper presents a highly efficient multimode multiplier supporting prime field, namely, polynomial field, and matrix-vector multiplications based on an asymmetric word-based Montgomery multiplication (MM) algorithm. The proposed multimode 128 ?? 32 b multiplier provides throughput rates of 441 and 511 Mb/s for 256-b operands over GF(P) and GF(2n) at a clock rate of 100 MHz, respectively. With 21 930 additional gates for Advanced Encryption Standard (AES), the multiplier is extended to provide 1.28-, 1.06-, and 0.91-Gb/s throughput rates for 128-, 192-, and 256-b keys, respectively. The comparison result shows that the proposed integration architecture outperforms others in terms of performance and efficiency for both AES and MM that is essential in most public-key cryptosystems.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83577
    Appears in Collections:[電機工程學系] 期刊論文
    [電腦與通訊科技研發中心] 期刊論文
    [資訊工程學系] 期刊論文

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