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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83687

    Title: A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification
    Authors: C.-H. Lin;Y.-C. Chang;W.-C. Huang;W.-C. Lai;C.-T. Chiu;J.-M. Wu;S.-H. Hsu;C.-M. Huang;C.-C. Yang;S.-L. Chen
    教師: 吳仁銘
    Date: 2010
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, Paris, May 30 2010-June 2 2010, Pages 1061 - 1064
    Keywords: serializer
    Abstract: This paper proposes a packet-based verification platform with serial link interface for emulating the hardware of the heterogeneous IPs before tape out. With the serial link interface Serializer/Deserializer (SerDes) added between IPs, significant amount of pin counts can be reduced in the platform. An adapter is inserted between IP and SerDes to convert parallel bus into packets and handle the handshaking. Under our proposed adapter architecture and handshaking scheme, the limitation on the number of the master adapter is eliminated compared with Bus-based Advanced High-performance Bus (AHB) architecture. Simulation results show the data transfer through our proposed architecture works correctly without the limitation on the number of masters. With the proposed adapter and SerDes architecture, the number of required signals in the interconnect is reduced from 79 to two for the AHB bus.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83687
    Appears in Collections:[電機工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文
    [通訊工程研究所] 會議論文

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