National Tsing Hua University Institutional Repository:A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology
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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology


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    题名: A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology
    作者: Yu-Hao Hsu;Yang-Syu Lin;Ching-Te Chiu;Jen-Ming Wu;Shuo-Hung Hsu;Fan-Ta Chen;Min-Sheng Kao;YarSun Hsu
    教師: 吳仁銘
    日期: 2010
    出版者: Institute of Electrical and Electronics Engineers
    關聯: Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, Paris, May 30 2010-June 2 2010
    关键词: 32Gbps
    IC
    CMOS
    摘要: In this paper, a low propagation delay, low power, and area-efficient 4×4 load-balanced switch circuit for feedbackbased system is presented. In this periodic and deterministic switch, only two DFFs are used to implement a pattern generator which is a O(N3) hardware complexity in traditional matching algorithm based N×N switch. For packet reordering, a feedback path is established in series of symmetric patterns. As comparing with commercial switch systems, we implement a 4×4 switch IC directly in high speed domain without the use of SERDES interfaces to achieve low propagation delay and high scalability. In CML output buffer, PMOS active load and active back-end termination are introduced. A stacked current source and symmetric topology in CML-DFF are adopted. From our results, this work efficiently deducted 28ns propagation delay, 80% area and 80% power introduced by the SERDES interface. The throughput rate is up to 32Gbps (8Gbps/Ch).
    相関连結: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83688
    显示于类别:[電機工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文
    [通訊工程研究所] 會議論文

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