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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A self-testing and calibration method for embedded successive approximation register ADC

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83912

    Title: A self-testing and calibration method for embedded successive approximation register ADC
    Authors: X.-L. Huang;P.-Y. Kang;H.-M. Chang;J.-L. Huang;Y.-F. Chou;Y.-P. Lee;D.-M. Kwai;C.-W. Wu
    教師: 吳誠文
    Date: 2011
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: 16th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, JAPAN, JAN 25-28, 2011
    Keywords: mixed-signal testing
    ADC testing
    ADC calibration
    SoC testing
    successive approximation register (SAR) ADC
    Abstract: This paper presents a self-testing and calibration method for the embedded successive approximation register (SAR) analog-to-digital converter (ADC). We first propose a low cost design-for-test (DfT) technique which tests a SAR ADC by characterizing its digital-to-analog converter (DAC) capacitor array. Utilizing DAC major carrier transition testing, the required analog measurement range is just 4 LSBs; this significantly lowers the test circuitry complexity. Then, we develop a fully-digital missing code calibration technique that utilizes the proposed testing scheme to collect the required calibration information. Simulation results are presented to validate the proposed technique.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83912
    Appears in Collections:[電機工程學系] 會議論文
    [電腦與通訊科技研發中心] 會議論文
    [資訊工程學系] 會議論文

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