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    顯示項目1-25 / 18482. (共740頁)
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    日期題名作者
    2008 A 0.13mm CMOS 4-channel timed array transmitter chipset with sub-200ps switches and all-digital timing circuitry Z. Safarian; T. Chu; H. Hashemi
    2008 A 0.18-μm CMOS Balanced Amplifier for 24-GHz Applications Jin, Jun-De; Hsu, Shawn S. H.
    2007 0.25um BCD 製程之BJT元件直流特性分析 李建融; Jian-Rong Li; J.Gong
    2008 0.25微米BCD製程之高電流增益BJT元件與JFET元件設計 林彥宏; Jeng Gong; Yen-Hung Lin
    2007 A 0.26-mu m(2) U-Shaped nitride-based programming cell on pure 90-nm CMOS technology Lai HC; Cheng KY; King YC; Lin CJ
    2007 A 0.26-μm2 U-Shaped Nitride-Based Programming Cell on Pure 90-nm CMOS Technology Lai, Han-Chao; Cheng, Kai-Yuan; King, Ya-Chin; Lin, Chrong-Jung
    2010 A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications M.-F. Chang; S.-M. Yang; C.-W. Liang; C.-C. Chiang; P.-F. Chiu; K.-F. Lin; Y.-H. Chu; W.-C. Wu; H. Yamauchi
    2004 0.35um SiGe BiCMOS 5.2 GHz 射頻主動電感的設計與應用 黃文彬; Wen-Pin Huang; Jeng Gong
    2007 0.35um製程之橫向金氧半場效電晶體特性分析 薛婉君; Jeng Gong; Wan-Jyun Syue
    2009 0.35和0.25微米BCD製程之橫向式蕭特基二極體元件設計 黃建豪; Huang, Chien-Hao; Gong, Jeng; Huang, Chin-Fang
    2012 A 0.5V 4Mb Logic-Process Compatible Embedded Resistive RAM (ReRAM) in 65nm CMOS Using Low Voltage Current-Mode Sensing Scheme with 45ns Random Read Time Meng-Fan Chang; Che-Wei Wu; Chia-Cheng Kuo; Shin-Jang Shen; Ku-Feng Lin; Shu-Meng Yang; Ya-Chin King; Chorng-Jung Lin; Yu-Der Chih
    2011 A 0.6V CMOS Image Sensor with in-Pixel Biphasic Current Driver for Biomedical Application Chin-Lin Lee; Chih-Cheng Hsieh
    2010 A 0.7-V CMOS Operational Transconductance Amplifier with Bulk-Driven Technique M.-H. Shen; Y.-S. Wu; G.-H. Ke; P.-C. Huang
    2005 1 Tbits/in.^2 非暫存式資料儲存:靜電力掃瞄探針陣列晶片之設計與製作(I) 盧向成
    2003 A 1  3W Grid-Connection PV Power Inverter with APF Based on Nonlinear Programming and FZPD Algorithm T.-F. Wu; C.-L. Shen; H.-S. Nei; J.-Y Chiu
    2002 A 1  3W Grid-Connection PV Power Inverter with Partial Active Power Filter T.-F. Wu; C.-L. Shen; C –H. Chang; J.-Y Chiu
    1989 A 1-subcycle parallel thinning algorithm for producing perfect 8-curves and obtaining isotropic skeleton of an L-shape pattern Chen, Y.-S.; Hsu, W.-H.
    2008 A 1-V 45-GHz balanced amplifier with 21.5-dB gain using 0.18-mu m CMOS technology Jin, Jun-De; Hsu, Shawn S. H.
    2008 A 1-V CMOS pseudo-differential amplifier with multiple common-mode stabilization and frequency compensation loops Meng-Hung Shen; Po-Hsiang Lan; Po-Chiun Huang
    2009 A 1-V Fully Differential Amplifier with Buffered Nested-Miller Compensation M.-H. Shen; P.-M. Wang; L.-W. Wang; P.-C. Huang
    2004 A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications Huang, Yuan-Hao; Ma, Hsi-Pin; Liou, Ming-Luen; Chiueh, Tzi-Dar
    2004 A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications Yuan-Hao Huang; Hsi-Pin Ma; Ming-Luen Liou; Tzi-Dar Chiueh
    2006 A 1.2-V 0.25-/spl mu/m clock output pixel architecture with wide dynamic range and self-offset cancellation Lai,Cheng-Hsiao; King,Ya-Chin; Huang,Shi-Yu
    2006 A 1.2-V 0.25-mu m clock output pixel architecture with wide dynamic range and self-offset cancellation Lai CH; King YC; Huang SY
    2006 A 1.2-V 0.25-μm clock output pixel architecture with wide dynamic range and self-offset cancellation Lai,Cheng-Hsiao; King,Ya-Chin; Huang,Shi-Yu

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