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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  A 1.2-V 0.25-/spl mu/m clock output pixel architecture with wide dynamic range and self-offset cancellation


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12068


    Title: A 1.2-V 0.25-/spl mu/m clock output pixel architecture with wide dynamic range and self-offset cancellation
    Authors: Lai,Cheng-Hsiao
    King,Ya-Chin
    Huang,Shi-Yu
    教師: 黃錫瑜
    Date: 2006
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Sensors Journal, IEEE
    Volume 6, Issue 2, April 2006 Page(s):398 - 405
    Keywords: Sensors
    CMOS integrated circuits
    Clocks
    Transistors
    Photodiodes
    Comparators
    Electric inverters
    Logarithmic amplifiers
    Sensitivity analysis
    Abstract: A 10T/pixel CMOS digital pixel sensor with clock count output, ultra low supply voltage, and wide dynamic range is presented. The pixel fabricated by a standard 0.25-μm CMOS logic process comprises a reset transistor, a photo-diode, a comparator, and an inverter with pixel size of 9.4 × 9.4 μm2 and 24% fill factor. The amplified logarithmic output response similar to the light response of human eye is demonstrated in this work. The pixel can operate at a supply voltage as low as 1.2 V without affecting its output characteristics. The dynamic range of this cell limited by either the subsequent analog-to-digital circuit resolution or the rising and falling time of output clock is higher than 90 dB with an 8-bit resolution. c 2006 IEEE.
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12068
    Appears in Collections:[電機工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文

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