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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12526


    Title: A built-in timing parametric measurement unit
    Authors: Hsiao, Ming-Jun
    Huang, Jing-Reng
    Yang, Shao-Shen
    Chang, Tsin-Yuan
    教師: 張慶元
    Date: 2001
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Relation: Test Conference, 2001. Proceedings. International,30 Oct.-1 Nov. 2001 Page(s):315 - 322
    Keywords: Static random access storage
    Integrated circuit testing
    Phase locked loops
    Analog to digital conversion
    Multiplexing
    Abstract: A built-in parametric measurement circuit is proposed for time-interval measurement and setup/hold time measurement.The main idea is based on the dual-slope technique.The minimum resolution is set by resistor array configuration,which is 1/16 clock period in this paper and easily extendable to desired precision.The imperfectness,including the offset voltage and the settling time,is considered to improve the accuracy. Moreover a simple calibration method is proposed to reduce the measuring error.Experiments on the SRAM access time measurement and the register setup/hold time measurement show the practicality of the proposed unit.
    Relation Link: http://doi.ieeecomputersociety.org/10.1109/TEST.2001.966647
    http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12526
    Appears in Collections:[電機工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文

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