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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12530

    Title: A built-in parametric timing measurement unit
    Authors: Hsiao, Ming-Jun
    Huang, Jing-Reng
    Chang, Tsin-Yuan
    教師: 張慶元
    Date: 2004
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Relation: IEEE DESIGN & TEST OF COMPUTERS Volume: 21 Issue: 4 Pages: 322-330 Published: JUL-AUG 2004
    Keywords: Integrated circuit testing
    Built-in self test
    Automatic testing
    Integrated circuit layout
    CMOS integrated circuits
    Abstract: With the limited accessibility of individual SoC components, many research teams are trying to find an easy way to access SoC components for digital testing. A parametric timing measurement solution that uses self-timed techniques and delivers linearity and improved accuracy at low risk of measurement error is presented. This scheme can be placed anywhere on-chip that requires accurate timing information without complicated controlling sequences.
    Relation Link: http://www.ieee.org/portal/site
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12530
    Appears in Collections:[電機工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文

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