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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12609


    Title: A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design
    Authors: Wen-Wen Hsieh
    Po-Yuan Chen
    Chun-Yao Wang
    TingTing Hwang
    教師: 王俊堯
    黃婷婷
    Date: 2007
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
    Volume 26, Issue 12, Dec. 2007 Page(s):2222 - 2227
    Keywords: crosstalk
    integrated circuit design
    logic design
    microprocessor chips
    system buses
    adjacent wires
    bus transmission
    bus-encoding scheme
    crosstalk effect crosstalk elimination
    deassembler/assembler technique
    deep-submicrometer level
    dynamic instruction count
    high-performance processor design
    instruction/data commit rate
    instruction/data fetch rate
    on-chip buses
    prefetch process
    Abstract: A crosstalk effect leads to increases in delay and power consumption and, in the worst-case scenario, to inaccurate results. With the scale down of technology to deep-submicrometer level, the crosstalk effect between adjacent wires becomes more and more serious, particularly between long on-chip buses. In this paper, we propose a deassembler/assembler technique to eliminate undesirable crosstalk effects on bus transmission. By taking advantage of the prefetch process, where the instruction/data fetch rate is always higher than the instruction/data commit rate, the proposed method incurs almost no penalty in terms of dynamic instruction count. In addition, when the bus width is 128 b, the required number of extra bus wires is only 7 as compared to the 85 extra bus wires needed in the work of Victor and Keutzer.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12609
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文

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