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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Exploiting communication complexity for multilevel logic synthesis

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12618

    Title: Exploiting communication complexity for multilevel logic synthesis
    Authors: Hwang, T.-T.
    Owens, R.M.
    Irwin, M.J.
    教師: 黃婷婷
    Date: 1990
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: IEEE Transactions on Volume 9,Issue 10,Oct.1990 Page(s):1017-1027
    Keywords: circuit layout CAD
    logic CAD
    many-valued logics
    matrix algebra
    communication complexity minimisation
    computer aided design
    interconnect minimisation
    layout design
    lower bound
    multilevel logic synthesis
    synthesis program
    Abstract: A multilevel logic synthesis technique based on minimizing communication complexity is presented. This approach is believed to be viable because, for many types of circuits, the area needed is dominated by interconnections. By minimizing communication complexity and interconnect, area is reduced. This approach performs especially well for functions that are hierarchically decomposable (e.g., adders, parity generators, comparators, etc.). Unlike many other multilevel logic synthesis techniques, a lower bound can be computed to determine how well the synthesis was performed. A new multilevel logic synthesis program based on the techniques described for reducing communication complexity is presented
    Relation Link: http://ieeexplore.ieee.org/Xplore/dynhome.jsp
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12618
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文

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