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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Automatic interconnection rectification for SoC design verification based on the port order fault model

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12656

    Title: Automatic interconnection rectification for SoC design verification based on the port order fault model
    Authors: Wang,Chun-Yao
    教師: 王廷基
    Date: 2003
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
    Volume 22, Issue 1, Jan. 2003 Page(s):104 - 114
    Keywords: Systems analysis
    Electric connectors
    Electric fault currents
    Integrated circuit layout
    Mathematical models
    Abstract: Embedded cores are being increasingly used in large system-on-a-chip (SoC) designs. The high complexity of SoC designs lead the design verification to be a challenge for system integrators. This paper presents an automatic interconnection rectification (AIR) technique based on the port order fault model to detect, diagnose, and correct the misplacements of interconnection that occurred in the integration of a SoC design automatically. The experiments are conducted on combinational and sequential benchmarks. Experimental results show that the AIR can correct the misplaced interconnection exactly within reasonable efforts and, therefore, accelerates the integration verification of SoC designs.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12656
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文

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