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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  An automorphic approach to verification pattern generation for SoC design verification using port-order fault model


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12662


    Title: An automorphic approach to verification pattern generation for SoC design verification using port-order fault model
    Authors: Wang,Chun-Yao
    Tung,Shing-Wu
    Jou,Jing-Yang
    教師: 王俊堯
    Date: 2002
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
    Volume 21, Issue 10, Oct. 2002 Page(s):1225 - 1232
    Keywords: Integrated circuit testing
    Microprocessor chips
    Integrated circuit layout
    Mathematical models
    Response time
    Design for testability
    Theorem proving
    Iterative methods
    Abstract: Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model was proposed. It has been used for verifying core-based designs and the corresponding verification pattern generation has been developed. Here, the authors present an automorphic technique to improve the efficiency of the automatic verification pattern generation (AVPG) for SoC design verification based on the POF model. On average, the size of pattern sets obtained on the ISCAS-85 and MCNC benchmarks are 45% smaller and the run time decreases 16% as compared with the previous results of AVPG.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12662
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文

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