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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Multilevel circuit clustering for delay minimization


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12678


    Title: Multilevel circuit clustering for delay minimization
    Authors: Sze, C.N.
    Ting-Chi Wang
    Wang, L.-C.
    教師: 王廷基
    Date: 2004
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
    Volume 23, Issue 7, July 2004 Page(s):1073 - 1085
    Keywords: VLSI
    circuit layout CAD
    circuit optimisation
    delays
    field programmable gate arrays
    graph theory
    integrated circuit layout
    minimisation
    delay minimization
    graph contraction
    lower-level clustering
    multilevel circuit clustering
    partitioning
    performance optimization
    physical design
    recursive clustering step
    single-level circuit clustering algorithm
    timing optimization
    very large scale integration
    Abstract: In this paper, an effective algorithm is presented for multilevel circuit clustering for delay minimization, and is applicable to hierarchical field programmable gate arrays. With a novel graph contraction technique, which allows some crucial delay information of a lower-level clustering to be maintained in the contracted graph, our algorithm recursively divides the lower-level clustering into the next higher-level one in a way that each recursive clustering step is accomplished by applying a modified single-level circuit clustering algorithm based on . We test our algorithm on the two-level clustering problem and compare it with the latest algorithm in . Experimental results show that our algorithm achieves, on average, 12% more delay reduction when compared to the best results (from TLC with full node-duplication) in . In fact, our algorithm is the first one for the general multilevel circuit clustering problem with more than two levels.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12678
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文

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