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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12716

    Title: Circuit optimization by rewiring
    Authors: Chang,Shih-Chieh
    van Ginneken, Lukas P.P.P.
    Date: 1999
    Publisher: Institute of Electrical and Electronics Engineers Computer Society
    Keywords: Combinatorial circuits
    Logic design
    Electric wiring
    Boolean functions
    Logic gates
    Industrial applications
    Mathematical transformations
    Abstract: This paper presents a very efficient optimization method suitable for multilevel combinational circuits. The optimization is based on incremental restructuring of a circuit through a sequence of additions and removals of redundant wires. Our algorithm applies the techniques of Automatic Test Pattern Generation (ATPG), which can efficiently detect redundancies. During the ATPG process, certain nodes in the circuit must have particular logic assignments for a test to exist. Based on the properties of these mandatory assignments, we have developed theorems to eliminate unnecessary wire redundancy checking. This results in significant performance improvement. The fast run time and the excellent scaling to large circuits make our Boolean optimization method practical for industrial applications.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12716
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文

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