Much research effort has been invested in automatic synthesis of leaf cell layout for CMOS VLSI design in the past decade. Most of them (includes one by the authors  base their layouts on the style proposed by Uehara and Van Cleemput  in 1981 when only one metal layer was available from most processing technologies. Presently, we have more metal layers for interconnection. Therefore, the issue of layout (or architecture) deserves more investigation. We propose in this paper a new layout style that enables either an automatic layout synthesizer or a layout designer to take full advantage of the second metal layer available from today's technology. Our style not only facilitates power/ground diffusion overlapping but also simplifies the intra-cell routing problem by having power/ground in the middle and routing in the upper and the lower constraint-free regions. We have implemented an automatic leaf cell layout synthesizer, called THEDA.P, based on the proposed style. Using the same transistor placement algorithm, THEDA.P outperforms a synthesizer based on 's style by almost 20% in layout compactness across a wide range of SSI circuits. THEDA.P has been used to build a standard cell library that was previously handcrafted. Results from designing two modules show that THEDA.P's layout quality is very competitive.