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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  An Efficient Layout Style for 2-Metal CMOS Leaf Cells and Its Automatic Synthesis


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12823


    Title: An Efficient Layout Style for 2-Metal CMOS Leaf Cells and Its Automatic Synthesis
    Authors: Hwang,Chi Yi
    Hsieh,Yung-Ching
    Lin,Youn-Long
    Hsu,Yu-Chin
    Date: 1993
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Keywords: Electric network synthesis
    Integrated circuit layout
    VLSI circuits
    CMOS integrated circuits
    Computer aided design
    Algorithms
    Abstract: Much research effort has been invested in automatic synthesis of leaf cell layout for CMOS VLSI design in the past decade. Most of them (includes one by the authors [1] base their layouts on the style proposed by Uehara and Van Cleemput [2] in 1981 when only one metal layer was available from most processing technologies. Presently, we have more metal layers for interconnection. Therefore, the issue of layout (or architecture) deserves more investigation. We propose in this paper a new layout style that enables either an automatic layout synthesizer or a layout designer to take full advantage of the second metal layer available from today's technology. Our style not only facilitates power/ground diffusion overlapping but also simplifies the intra-cell routing problem by having power/ground in the middle and routing in the upper and the lower constraint-free regions. We have implemented an automatic leaf cell layout synthesizer, called THEDA.P, based on the proposed style. Using the same transistor placement algorithm, THEDA.P outperforms a synthesizer based on [2]'s style by almost 20% in layout compactness across a wide range of SSI circuits. THEDA.P has been used to build a standard cell library that was previously handcrafted. Results from designing two modules show that THEDA.P's layout quality is very competitive.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12823
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [清大/工研院聯合研究中心] 期刊論文

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