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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12824


    Title: LiB: A CMOS cell compiler
    Authors: Hsieh,Yung-Ching
    Hwang,Chi-Yi
    Lin,Youn-Long
    Hsu,Yu-Chin
    Date: 1991
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Keywords: Integrated Circuits
    CMOS
    Computer Aided Design
    VLSI - Computer Aided Design
    Transistors
    Computer Programming
    Algorithms
    Diffusion
    Abstract: An automatic layout generation system, called LiB, for the small-scale integrated (SSI) cells used in CMOS VLSI design, is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a mask layout in CIF. The layout style is a modification of that proposed by T. Uehara, and W. M. van Cleemput (IEEE Trans. Comput., vol. C-30, pp. 305-312, May 1981). An optimal transistor chaining algorithm has been developed to derive a transistor placement with a minimum number of diffusion separations. To meet the cell height constraint, large transistors are folded into multiple columns algorithmically. The whole cell is divided into five routing regions. Two are on the diffusion island and the others are rectilinear-shaped routing channels. A graph-theoretic method for selecting nets (subnets) for routing on the diffusion island is proposed. A global routing algorithm has been developed to assign the remaining nets to the three rectilinear channels. For the detailed routing, SILK, a simulated evolution router, is employed. LiB can be used as a cell library builder or as a subsystem of a random logic module generator. Users can alternate LiB's layout using a symbolic editor.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12824
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [清大/工研院聯合研究中心] 期刊論文

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