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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Performance-driven interconnection optimization for microarchitecture synthesis

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12825

    Title: Performance-driven interconnection optimization for microarchitecture synthesis
    Authors: Jiang,Yi-Min
    Hwang,Ting Ting
    教師: 黃婷婷
    Date: 1994
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: IEEE Transactions on Volume 13,Issue 2,Feb.1994 Page(s):137-149
    Keywords: Electric network synthesis
    Large scale systems
    Data transfer
    Linear programming
    Constraint theory
    Heuristic programming
    Storage allocation
    Computer architecture
    Mathematical models
    Abstract: This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12825
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [清大/工研院聯合研究中心] 期刊論文

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