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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Effective Enforcement of Path Delay Constraints in Performance-Driven Placement

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12827

    Title: Effective Enforcement of Path Delay Constraints in Performance-Driven Placement
    Authors: Chou,Yih-Chih
    Date: 2002
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Keywords: Integrated circuit layout
    Constraint theory
    Flip flop circuits
    Program processors
    Response time
    Set theory
    Abstract: We propose a performance-driven cell placement method based on a modified force-directed approach. A pseudolink is added to connect the source and sink flip-flops of every critical path to enforce their closeness. Given user-specified input-output pad locations at the chip boundaries and starting with all core cells in the chip center, we iteratively move one cell at a time to its force-equilibrium location assuming all other cells are fixed. The process stops when no cell can be move farther than a threshold distance. Next, cell rows are formed one at a time starting from the top and bottom. After forming these two cell rows (top/bottom), all remaining movable core cells' force-equilibrium locations are updated. The row-formation-and-update process continues until all rows are formed and, hence, a legal placement is obtained. We have integrated the proposed approach into an industrial automatic placement-and-route flow. Experimental results on benchmark circuits up to 191-K cell (500-K gate) show that the critical path delay can be improved by as much as 17%. Our layout quality is independent of initial placement. We also study the effect on both layout quality and central processing unit time consumption due to the amount of pseudolinks added. We found that the introduction of pseudolink indeed significantly improves the layout quality. We also empirically demonstrated that the proposed approach is effective in reducing the total half-perimeter wirelength metric.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12827
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [清大/工研院聯合研究中心] 期刊論文

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