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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Timing-driven soft-macro resynthesis method in interaction with chip floorplanning


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12828


    Title: Timing-driven soft-macro resynthesis method in interaction with chip floorplanning
    Authors: Su,Hsiao-Pin
    Wu,Allen C. -H
    Lin,Youn-Long
    Date: 1999
    Publisher: ACM
    Keywords: Microprocessor chips
    Electric network analysis
    Electric network synthesis
    Integrated circuit layout
    Constraint theory
    Abstract: In this paper, we present a complete chip design method which incorporates a soft-macro resynthesis method in interaction with chip floorplanning for area and timing improvements. We develop a timing-driven design flow to exploit the interaction between HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing constraint which is guided by the post-layout timing information. The goal is to produce area-efficient designs while satisfying the timing constraints. Experiments on a number of industrial designs have demonstrated that by effectively relaxing the timing constraint of the non-critical modules and tightening the timing constraint of the critical modules, a design can achieve 13% to 30% timing improvements with little to no increase in chip area.
    Relation Link: http://portal.acm.org/citation.cfm?doid=309847.309926
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12828
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [清大/工研院聯合研究中心] 期刊論文

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