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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Fast transistor-chaining algorithm for CMOS cell layout


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12829


    Title: Fast transistor-chaining algorithm for CMOS cell layout
    Authors: Hwang,Chi-Yi
    Hsieh,Yung-Ching
    Lin,Youn-Long
    Hsu,Yu-Chin
    Date: 1990
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Keywords: Integrated Circuits
    Digital
    Layout
    Semiconductor Devices
    MOS
    Computer Aided Design
    CMOS
    Abstract: A fast algorithm is proposed for the transistor-chaining problem in CMOS functional cell layout based on the layout style of T. Uehara and W. M. vanCleemput (1981). The algorithm takes a transistor-level circuit schematic and outputs a minimum set of transistor chains. Possible diffusion abutments between the transistor pairs are modeled as a bipartite graph. A depth-first search algorithm is used to search for the optimal chaining. Theorems on the set of branches that needs to be explored at each node of the search tree are derived. A theoretical lower bound on the size of the chain set is also derived. This bound enables one to prune the search tree efficiently. The algorithm has been implemented and tested and is able to find optimal solutions almost instantly for all the cases from the literature that were examined.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12829
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [清大/工研院聯合研究中心] 期刊論文

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