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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Row-based cell placement method that utilizes circuit structural properties

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12830

    Title: Row-based cell placement method that utilizes circuit structural properties
    Authors: Tsay,Yu-Wen
    Date: 1995
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Keywords: Integrated circuit layout
    Computer aided design
    Simulated annealing
    Application specific integrated circuits
    Computational complexity
    Abstract: We propose a cell placement method for row-based integrated circuit layout. The proposed method cleverly utilizes the structural properties of the circuits. It first extracts strongly connected subcircuits, called cones, from the circuit and then groups small cones, called fragments, to reduce the number of cones. The algorithm then performs a macro-cell placement, treating each cone as a soft macro. Next, it maps the resulting macro-cell placement into a row-based placement. Finally, it applies a simulated-annealing procedure to refine the row-based placement. It is able to produce, in a shorter period of CPU time, a higher quality placement compared to classical simulated-annealing-based placement methods as demonstrated by some experimental results on the MCNC benchmarks.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12830
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [清大/工研院聯合研究中心] 期刊論文

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