English  |  正體中文  |  简体中文  |  Items with full text/Total items : 54367/62174 (87%)
Visitors : 10040870      Online Users : 132
RC Version 6.0 © Powered By DSPACE, MIT. Enhanced by NTHU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Combining technology mapping and placement for delay-minimization in FPGA designs


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12831


    Title: Combining technology mapping and placement for delay-minimization in FPGA designs
    Authors: Chen,Chau-Shen
    Tsay,Yu-Wen
    Hwang,TingTing
    Wu,Allen C. H.
    Lin,Youn-Long
    教師: 黃婷婷
    Date: 1995
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: IEEE Transactions on Volume 14,Issue 9,Sept.1995 Page(s):1076-1084
    Keywords: Application specific integrated circuits
    Integrated circuit layout
    Random access storage
    Logic gates
    Iterative methods
    Boolean functions
    Mathematical techniques
    Algorithms
    Computer aided logic design
    Abstract: We combine technology mapping and placement into a single procedure, M.map, for the design of RAM-based FPGA's. Iteratively, M.map maps several subnetworks of a Boolean network into a number of CLB's on the layout plane simultaneously. For every output node of the unmapped portion of the Boolean network, many ways of mapping are possible. The choice of which mapping to be used depends not only on the location of the CLB into which the output node will be mapped but also on its interconnection with those already mapped CLB's. To deal with such a complicated interaction among multiple output nodes of a Boolean network, multiple ways of mappings and multiple number of CLB's any greedy algorithm will be insufficient. Therefore, we use a bipartite weighted matching algorithm in finding a solution that takes the global information into consideration. With the availability of the partial placement information, M.map is able to minimize the routing delay in addition to the number of CLB's. Experimental results on a set of benchmarks demonstrate that M.map is indeed effective and efficient.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12831
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [清大/工研院聯合研究中心] 期刊論文

    Files in This Item:

    File Description SizeFormat
    2030207010013.pdf910KbAdobe PDF947View/Open


    在NTHUR中所有的資料項目都受到原著作權保護,僅提供學術研究及教育使用,敬請尊重著作權人之權益。若須利用於商業或營利,請先取得著作權人授權。
    若發現本網站收錄之內容有侵害著作權人權益之情事,請權利人通知本網站管理者(smluo@lib.nthu.edu.tw),管理者將立即採取移除該內容等補救措施。

    SFX Query

    與系統管理員聯絡

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback