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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Combining technology mapping and placement for delay-minimization in FPGA designs

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12831

    Title: Combining technology mapping and placement for delay-minimization in FPGA designs
    Authors: Chen,Chau-Shen
    Wu,Allen C. H.
    教師: 黃婷婷
    Date: 1995
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Relation: IEEE Transactions on Volume 14,Issue 9,Sept.1995 Page(s):1076-1084
    Keywords: Application specific integrated circuits
    Integrated circuit layout
    Random access storage
    Logic gates
    Iterative methods
    Boolean functions
    Mathematical techniques
    Computer aided logic design
    Abstract: We combine technology mapping and placement into a single procedure, M.map, for the design of RAM-based FPGA's. Iteratively, M.map maps several subnetworks of a Boolean network into a number of CLB's on the layout plane simultaneously. For every output node of the unmapped portion of the Boolean network, many ways of mapping are possible. The choice of which mapping to be used depends not only on the location of the CLB into which the output node will be mapped but also on its interconnection with those already mapped CLB's. To deal with such a complicated interaction among multiple output nodes of a Boolean network, multiple ways of mappings and multiple number of CLB's any greedy algorithm will be insufficient. Therefore, we use a bipartite weighted matching algorithm in finding a solution that takes the global information into consideration. With the availability of the partial placement information, M.map is able to minimize the routing delay in addition to the number of CLB's. Experimental results on a set of benchmarks demonstrate that M.map is indeed effective and efficient.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12831
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [清大/工研院聯合研究中心] 期刊論文

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