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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12839


    Title: PLS: A scheduler for pipeline synthesis
    Authors: Hwang,Cheng-Tsung
    Hsu,Yu-Chin
    Lin,Youn-Long
    Date: 1993
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Keywords: Pipeline processing systems
    Optimization
    Scheduling
    Algorithms
    Digital signal processing
    Abstract: Pipelining is an effective method to optimize the execution of a loop, especially for digital signal processing (DSP) applications where data enter a circuit regularly. Although throughout and delay are two important optimization criteria, previous work emphasizes mainly on the throughout. We show that the delay time of executing an iteration of a loop has a strong relationship with the cost of the registers and the controller. We iteratively use a forward scheduling and a backward scheduling to achieve this purpose.
    Relation Link: http://webservices.ieee.org/pindex_basic.html
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12839
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [清大/工研院聯合研究中心] 期刊論文

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