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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  High-speed easily testable Galois-field inverter


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12896


    Title: High-speed easily testable Galois-field inverter
    Authors: Huang,Chih-Tsun
    Wu,Cheng-Wen
    Date: 2000
    Publisher: Institute of Electrical and Electronics Engineers Inc
    Keywords: Galois fields
    VLSI
    cryptography
    design for testability
    error correction codes
    logic gates
    logic testing
    systolic arrays
    Abstract: Galois field (GF) computation is important in applications such as error-control coding, switching theory, and cryptography. In GF, division and inversion operations are much harder to implement in digital logic as compared with multiplication and addition operations so far as performance and hardware complexity is concerned. Although several VLSI structures for division or inversion have been proposed in the past, most of them have complex routing, nonmodular architectures, and low testability. Testability especially is an increasing concern in VLSI design. In this paper, C-testable bit-level systolic arrays for GF(2m) inversion are presented. We propose a counter-free extended Euclidean algorithm for GF inversion. Based on the algorithm, we obtain efficient systolic GF inverters, which are extendible to GF dividers. Both the bit-parallel and bit-serial inverters proposed are shown to be easily testable. For example, the bit-serial inverter requires only four test patterns regardless of the field size (or number of cells). High testability is a key advantage for the proposed GF inverters, especially in core-based VLSI system chips
    Relation Link: http://ieeexplore.ieee.org/Xplore/dynhome.jsp
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12896
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文

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