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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/12897


    Title: RAMSES: A fast memory fault simulator
    Authors: Wu,Chi-Feng
    Huang,Chih-Tsun
    Wu,Cheng-Wen
    Date: 1999
    Publisher: Institute of Electrical and Electronics Engineers Computer Society
    Keywords: automatic testing
    circuit simulation
    computational complexity
    fault simulation
    integrated circuit testing
    integrated memory circuits
    random-access storage
    Abstract: In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some well-known memory fault models, the algorithm that we developed ensures that new fault models can be included easily by adding new fault descriptors instead of modifying the algorithm or program. With RAMSES, the time complexity of memory fault simulation is improved from O(N3) to O(N2), where N is the memory capacity in terns of bits. Our approach requires only a small amount of extra memory space. Simulation results by RAMSES show that running the proposed cocktail-March tests can significantly reduce the test time. With the help of RAMSES, an efficient test algorithm called March-CW was developed for word-oriented memories
    Relation Link: http://ieeexplore.ieee.org/Xplore/dynhome.jsp
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/12897
    Appears in Collections:[資訊工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文

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