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    NTHUR > College of Electrical Engineering and Computer Science > Department of Electrical Engineering > EE Conference Papers >  Towards the logic defect diagnosis for partial-scan designs


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13021


    Title: Towards the logic defect diagnosis for partial-scan designs
    Authors: Shi-Yu Huang
    Teacher: 黃錫瑜
    Date: 2001
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
    30 Jan.-2 Feb. 2001 Page(s):313 - 318
    Keywords: VLSI
    full-scan
    partial-scan
    IC
    Abstract: Local defect diagnosis is a critical yet challenging process in VLSI manufacturing. It involves the identification of the defect spots in a logic IC that fail testing. In the last decade, algorithms for diagnosis have progressed significantly and the results are showing promise for full-scan designs. In this paper, we first review several classical algorithms such as fault dictionary based analysis and effect cause analysis. Then, we discuss several diagnosis algorithms borrowed from the design debugging techniques. These algorithms do not require a pre-determined fault model, and thus, are more flexible and applicable to ICs in which the defects do not behave like common stuck-at or bridging faults. Finally, we will probe the possibility of extending these algorithms to designs with only partial-scan support.
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13021
    Appears in Collections:[Department of Electrical Engineering] EE Conference Papers
    [Design Technology Center ] DTC Conference Papers

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