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    NTHUR > College of Electrical Engineering and Computer Science > Department of Electrical Engineering > EE Conference Papers >  Power estimation strategies for a low-power security processor


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13028


    Title: Power estimation strategies for a low-power security processor
    Authors: Yen-Fong Lee
    Shi-Yu Huang
    Sheng-Yu Hsu
    I-Ling Chen
    Cheng-Tao Shieh
    Jian-Cheng Lin
    Shih-Chieh Chang
    Teacher: 黃錫瑜
    Date: 2005
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Relation: Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
    Volume 1, 18-21 Jan. 2005 Page(s):367 - 371 Vol. 1
    Keywords: Power estimation
    PowerMixer
    SPICE
    Abstract: In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the logic part, we present a highly accurate tool, called PowerMixer. This tool is a refinement of the so-called mixed-level methodology that combines the accuracy of quick SPICE and the speed of gate-level simulation. A grouping scheme is proposed so as to improve the accuracy for design blocks as large as 100K gates. For the memory part, we investigated the power consuming behavior of memories and point out the potential problems associated with the current commercial design flow. These tools, along with a previously published static peak power estimation method (Hsieh et al., 2004), jointly provide an evaluation platform for the power optimization and verification process of our security processor in a practical way.
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13028
    Appears in Collections:[Department of Electrical Engineering] EE Conference Papers
    [Design Technology Center ] DTC Conference Papers

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