National Tsing Hua University Institutional Repository:Power estimation strategies for a low-power security processor
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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  Power estimation strategies for a low-power security processor


    题名: Power estimation strategies for a low-power security processor
    作者: Yen-Fong Lee
    Shi-Yu Huang
    Sheng-Yu Hsu
    I-Ling Chen
    Cheng-Tao Shieh
    Jian-Cheng Lin
    Shih-Chieh Chang
    教師: 黃錫瑜
    日期: 2005
    出版者: Institute of Electrical and Electronics Engineers Inc.
    關聯: Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
    Volume 1, 18-21 Jan. 2005 Page(s):367 - 371 Vol. 1
    关键词: Power estimation
    摘要: In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the logic part, we present a highly accurate tool, called PowerMixer. This tool is a refinement of the so-called mixed-level methodology that combines the accuracy of quick SPICE and the speed of gate-level simulation. A grouping scheme is proposed so as to improve the accuracy for design blocks as large as 100K gates. For the memory part, we investigated the power consuming behavior of memories and point out the potential problems associated with the current commercial design flow. These tools, along with a previously published static peak power estimation method (Hsieh et al., 2004), jointly provide an evaluation platform for the power optimization and verification process of our security processor in a practical way.
    显示于类别:[電機工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文


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