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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  Accurate RT-level power estimation using up-down encoding


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/13039


    Title: Accurate RT-level power estimation using up-down encoding
    Authors: Ming-Yi Sum
    Shi-Yu Huang
    Chia-Chien Weng
    Kai-Shuang Chang
    教師: 黃錫瑜
    Date: 2004
    Publisher: Institute of Electrical and Electronics Engineers Inc.
    Relation: Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
    Volume 1, 6-9 Dec. 2004 Page(s):69 - 72 vol.1
    Keywords: RT-level
    cycle-by-cycle
    up-down encoding
    Abstract: RT-level power estimation is to quickly predict the total switching activity in a logic design without resorting to the time-consuming gate-level simulation. We propose an up-down encoding scheme in conjunction with linear approximation to improve the estimation accuracy. In order to take into account the temporal correlation in the input patterns, we use a cycle-by-cycle modeling scheme. On top of it, each primary input is further encoded into two binary variables to faithfully reflect its switching behavior. The proposed method has been realized as a tool that can fit into the commercial design flow and tested by a number of datapath design blocks. Experimental results show that the estimation error is only 1.3 %.
    URI: http://nthur.lib.nthu.edu.tw/handle/987654321/13039
    Appears in Collections:[電機工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文

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