The electrical characteristics of metal-ferroelectric-insulator-silicon (MFIS) structures are studied. The ferroelectric layer is lead-zirconate-titanate (PZT) and the insulator layer is Ta2O5. The orientation of the C-V hysteresis loop depends on both the polarization of the ferroelectric layer and the trapped charges injected into the insulator layer. These two effects are opposite to each other. The C-V orientation is counterclockwise when the applied voltage is below 7 V and clockwise above 7 V. The C-V memory window first increases and then decreases with the applied sweep voltage. These phenomena are explained by the polarization and the charge trapping effects.